SSTL_3, V, defined in EIA/JESD ; SSTL_2, V, defined in EIA/ JESDB used in DDR among other things. SSTL_18, V, defined in. STUB SERIES TERMINATED. LOGIC FOR VOLTS (SSTL_2). EIA/JESD SEPTEMBER ELECTRONIC INDUSTRIES ALLIANCE. JEDEC Solid State . SSTL (JESD, JESDB, JESD). • HSTL (JESD). LVTTL and LVCMOS were developed as a direct result of technology scaling. With each reduction in.

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However, the drivers are connected directly onto the bus so there are no stubs present. NOTE 2 A 1. The third clause specifies the minimum required output characteristics of, and ac test conditions for, compliant outputs targeted for various application environments. In this non binding section we will show some derived applications.

Stub Series Terminated Logic

However a Class II buffer would dissipate more power due to its larger current drive and thus might require special cooling. Days after jsd8 of this standard in Mayit was brought to the attention of the sponsor that there were errors in Table 4. VTT is specified as being equal to 0. In order to meet the mV minimum requirement for VIN, a minimum of 8.

O rgan iz atio ns m ay ob tain perm issio n to rep rod uce a lim ited n um jeed8 er o f co pies thro ugh enterin g in to a licen se agreem en t.


However in order to provide a basis, the driver characteristics will be derived in terms of a typical 50? If the driver outputs are sized for this condition, then for all other VDDQ voltage applications, the resulting input signal will be larger than the minimum mV. This jess8 be expressed by equation-1 or jes8 The relationship of the different levels is shown in figure 1. While driver characteristics are derived from a 50?

If you have downloaded the jesdd8 prior to date of errata please reprint page 7. The ac values are chosen to indicate the levels at which the receiver must meet its timing specifications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint.

The dc values are chosen such that the final logic state is unambiguously defined, that is once the receiver input has crossed this value, the receiver will change to and maintain the new logic state. The driver specification now must guarantee that these values of VIN are obtained in the worst case conditions specified by this standard. An example is shown in figure 7. An example is shown in figure 8. AC test conditions may be measured under nominal voltage conditions as long as the supplier can demonstrate jedd8 analysis, that the device will meet its timing specifications under all supported voltage conditions.

The standard is particularly intended to improve operation in situations where 9g must be isolated jsd8 relatively large stubs. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between 9bb and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.


F or 9 rm ationcon tact: Typically the value of VREF is expected to be 0. JEDEC is the leading developer of standards for the solid-state industry, they have published over documents to date. In that case, the designer may decide to eliminate the series resistors entirely. Making this distinction is important for the design of high gain, differential, receivers that are required.

EIA JEDEC STANDARD jesdb-sstl_2_百度文库

However, in the case of VIH Max. See also figure 2. With a series resistor of 25?

Class I or Units V mV Notes 1 1 0. Viso Parameter Input clock signal offset voltage Viso variation Min.

In some standards this ratio equals 0. The system designer will be able to vary impedance levels, termination resistors and supply voltage and be able to calculate the effect on system voltage margins.